For high speed semiconductor devices, ultra-shallow junctions, low sheet resistance and abrupt lateral junctions are important to reduce short channel effects and to increase transistor saturation current in source drain extensions. To help form such shallow and low sheet resistance junctions, low energy implants and sharp spike anneals have been used to resolve the issues such as transient enhanced diffusion (TED), solid solubility, and channeling.
Spike anneal is typically performed by subjecting a semiconductor substrate having implanted dopants to temperature treatment in a rapid thermal processing (RTP) system. A typical annealing profile using RTP may involve ramping up to a target temperature, e.g. 1050° C., soaking the substrate at the target temperature for a period of time (which is generally referred to as “soak time”), and ramping down to a base temperature, e.g. 200° C.
As the wafers undergo the spike anneal process, the stability of the material to the annealing process, particularly for materials deposited at lower temperatures, may be critical to the device performance. More specifically, the dielectric films used for such applications should exhibit one or more of the following characteristics: relatively lower wet etch rate (such as when exposed to dilute HF); dielectric constant of 6.0 or less; good within wafer uniformity, conformality, or combinations thereof; resistance to gas phase processes (such as for example oxidative plasmas); and/or exhibits relatively little to no change in properties and film structure when subjected to a temperature spike anneal process compared to similar materials of its class.